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1 isl62881c, isl62881d caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. single-phase pwm regulator for imvp-6.5? mobile cpus and gpus isl62881c, isl62881d the isl62881c provides a complete solution for microprocessor and graphic processor core power supply with it?s integrated gate drive. based on intersil?s robust ripple regulator (r3?) technology, the pwm modulator compared to traditional modulators, has faster transient settling time, variable switching frequency during load transients and has improved light load efficiency with its ability to automatically change switching frequency. fully compliant with imvp6.5? , the isl62881c is easily configurable as a cpu or graphics v core controllers by offering: responds to dprslpvr signals by entering/exiting diode em ulations mode; reports regulator output current via the imon pin; senses current by using a discrete resistor or the inductor; over-temperature thermal compensation of dcr, using a single ntc thermistor; differential sensing to accurately monitor and adjust processor die voltage; minimizes body diode conduction loss in diode emulation mode with it?s adaptive body diode conduction time. need to aggressively reduce the output capacitor? the overshoot reduction function is user-selectable and can be disabled for those concerned about increased system thermal stress. maintaining all the isl62881c functions, the isl62881d offers vr_tt# function for thermal throttling control. it also offers the split lgate function to further improve light load efficiency. features ? precision core voltage regulation - 0.5% system accuracy over-temperature - enhanced load line accuracy ? supports multiple current sensing methods - lossless inductor dcr current sensing - precision resistor current sensing ? current monitor ? differential remote voltage sensing ? integrated gate driver ? split lgate driver to increase light-load efficiency (for isl62881d) ? adaptive body diode conduction time reduction ? user-selectable overshoot reduction function ? small footprint 28 ld 4x4 or 32 ld 5x5 tqfn package applications ? notebook core voltage regulator ? notebook gpu voltage regulator related literature ?see an1552 for evaluation board application note ?isl62881ccpueval2z user guide? ?see an1553 for evaluation board application note ?isl62881cgpueval2z user guide? load line regulation 0.80 0.81 0.82 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.90 0.91 10 12 14 16 18 20 22 i out (a) v out (v) 02468 v in = 19v v in = 12v v in = 8v march 8, 2010 fn7596.0
isl62881c, isl62881d 2 fn7596.0 march 8, 2010 ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # isl62881chrtz 62881c hrtz -10 to +100 28 ld 4x4 tqfn l28.4x4 isl62881cirtz 62881c irtz -40 to +100 28 ld 4x4 tqfn l28.4x4 ISL62881DHRTZ 62881d hrtz -10 to +100 32 ld 5x5 tqfn l32.5x5e notes: 1. add ?-t? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). inte rsil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl62881c , isl62881d . for more information on msl please see techbrief tb363 . pin configurations isl62881c (28 ld tqfn) top view isl62881d (32 ld tqfn) top view 1 28 2 3 4 5 6 7 21 20 19 18 17 16 15 27 26 25 24 23 22 8 9 10 11 12 13 14 gnd pad (bottom) v i d 6 v i d 4 v i d 3 v i d 2 vid0 d p r s l p v r vccp lgate phase ugate comp fb vw pgood rbias clk_en# v i d 5 v r _ o n vssp i s u m - i s u m + v i n i m o n v d d r t n vsen b o o t vid1 1 32 2 3 4 5 6 7 24 23 22 21 20 19 18 31 30 29 28 27 26 9101112131415 gnd pad (bottom) v r _ o n v i d 5 v i d 4 v i d 3 vid0 c l k _ e n # vccp lgatea phase gnd vw ntc rbias vr_tt# v i d 6 d p r s l p v r vssp i s u m - i s u m + v i n i m o n v d d v s e n vid1 8 comp fb pgood b o o t 16 r t n 17 ugate lgateb 25 v i d 2 pin function description isl62881c isl62881d symbol description 1 32 clk_en# open drain output to enable system pl l clock. it goes low 13 switching cycles after v core is within 10% of v boot . 2 1 pgood power-good open-drain output indicati ng when the regulator is able to supply regulated voltage. pull up externally with a 680 resistor to vccp or 1.9k to 3.3v. 3 2 rbias a resistor to gnd sets in ternal current reference. a 147k resistor sets the controller for cpu core application and a 47k resistor sets the co ntroller for gpu core application. - 3 vr_tt# thermal overload output indicator. - 4 ntc thermistor input to vr_tt# circuit. - 5 gnd signal common of the ic. unless otherwise stated, signals are referenced to the gnd pin. isl62881c, isl62881d
isl62881c, isl62881d 3 fn7596.0 march 8, 2010 4 6 vw a resistor from this pin to comp programs the switching frequency (8k gives approximately 300khz). 5 7 comp this pin is the output of the error amplif ier. also, a resistor ac ross this pin and gnd adjusts the overcurrent threshold. 6 8 fb this pin is the inverting input of the error amplifier. 7 9 vsen remote core voltage sense inpu t. connect to microprocessor die. 810rtnremote voltage sensin g return. connect to ground at microprocessor die. 9, 10 11, 12 isum- and isum+ droop current sense input. 11 13 vdd 5v bias power. 12 14 vin power stage supply voltage, used for feed-forward. 13 15 imon an analog output. imon outputs a cu rrent proportional to the regulator output current. 14 16 boot connect an mlcc capacitor across the boot and the phase pin. the boot capacitor is charged through an internal boot diod e connected from the vccp pin to the boot pin, each time the phase pin drops below vccp minus the voltage dropped across the internal boot diode. 15 17 ugate output of the high-side mosfet gate dr iver. connect the ugate pin to the gate of the high-side mosfet. 16 18 phase current return path for the high-side mosfet gate driver. connect the phase pin to the node consisting of the high-side mosfet source, the low-side mosfet drain, and the output inductor. 17 19 vssp current return path for the low-side mo sfet gate driver. connec t the vssp pin to the source of the low-side mosfet through a lo w impedance path, preferably in parallel with the traces connecting the lgate pins to the gates of the low-side mosfet. 18 - lgate output of the low-side mosfet gate driver. connect the lgate1 pin to the gate of the phase-1 low-side mosfet. - 20 lgatea output of the low-side mosfet gate driv er that is always acti ve. connect the lgatea pin to the gate of the low-side mosfet that is active all the time. - 21 lgateb another output of the low-side mosfet ga te driver. this gate driver will be pulled low when the dprslpvr pin logic is high. conn ect the lgateb pin to the gate of the low-side mosfet that is id le in deeper sleep mode. 19 22 vccp input voltage bias for the internal ga te drivers. connect +5 v to the vccp pin. decouple with at least 1f of an mlcc capacitor to the vssp pin. 20, 21, 22, 23, 24, 25, 26 23, 24, 25, 26, 27, 28 29 vid0, vid1, vid2, vid3, vid4, vid5, vid6 vid input with vid0 = lsb and vid6 = msb. 27 30 vr_on voltage regulator enable input. a high level logic signal on this pin enables the regulator. 28 31 dprslpvr deeper sleep enable signal. a high le vel logic signal on this pin indicates that the microprocessor is in deeper sleep mode. pad bottom the bottom pad is electr ically connected to the gnd pin inside the ic. it should also be used as the therma l pad for heat removal. pin function description (continued) isl62881c isl62881d symbol description isl62881c, isl62881d
isl62881c, isl62881d 4 fn7596.0 march 8, 2010 block diagram vid0 vid1 vid2 vid3 vid4 vid5 vid6 vr_on dprslpvr mode control dac and soft start rtn e/a fb idroop current sense isum+ isum- imon imon comp protection pgood clk_en# adj. ocp threshold vsen clock vw vin flt woc oc 2.5 x woc oc vin vdac modulator vin vdac comp vw comp pgood and clk_en# logic gnd vdd rbias 60a
isl62881c, isl62881d 5 fn7596.0 march 8, 2010 table of contents related literature . . . . . . . . . . . . . . . . . . . . . . 1 load line regulation . . . . . . . . . . . . . . . . . . . . 1 pin function description . . . . . . . . . . . . . . . . . 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . 6 thermal information . . . . . . . . . . . . . . . . . . . . 6 recommended operating conditions . . . . . . . . 6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 6 gate driver timing diagram. . . . . . . . . . . . . . . 9 simplified application circuits . . . . . . . . . . . . . 9 theory of operation . . . . . . . . . . . . . . . . . . . . 12 multiphase r3? modulator .............................. 12 diode emulation and period stretching.............. 13 start-up timing ............................................. 13 voltage regulation and load line implementation ........................................... 14 differential sensing ........................................ 16 ccm switching frequency ............................... 16 modes of operation ........................................16 dynamic operation......................................... 16 protections .................................................... 17 current monitor ............................................. 17 adaptive body diode conduction time reduction ............................................ 18 overshoot reduction function.......................... 18 key component selection . . . . . . . . . . . . . . . . 18 r bias ........................................................... 18 inductor dcr current-sensing network ............ 18 resistor current-sensing network .................. 20 overcurrent protection ................................... 21 load line slope............................................. 21 current monitor............................................. 21 compensator ................................................ 22 optional slew rate compensation circuit for 1-tick vid transition ............................... 24 voltage regulator thermal throttling ............... 24 layout guidelines . . . . . . . . . . . . . . . . . . . . . . 25 cpu application reference design bill of materials . . . . . . . . . . . . . . . . . . . . . . . 29 gpu application reference design bill of materials . . . . . . . . . . . . . . . . . . . . . . . 30 typical performance . . . . . . . . . . . . . . . . . . . . 32 revision history . . . . . . . . . . . . . . . . . . . . . . . 35 products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 package outline drawing l28.4x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 package outline drawing l32.5x5e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 isl62881c, isl62881d
isl62881c, isl62881d 6 fn7596.0 march 8, 2010 absolute maximum ratings thermal information supply voltage, vdd. . . . . . . . . . . . . . . . . . . .-0.3v to +7v battery voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . +28v boot voltage (boot) . . . . . . . . . . . . . . . . . . -0.3v to +33v boot to phase voltage (boot-phase) . . . . -0.3v to +7v(dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +9v(<10ns) phase voltage (phase) . . . . . -7v (<20ns pulse width, 10j) ugate voltage (ugate) . . . . . . . phase-0.3v (dc) to boot . . . . . . . . . phase-5v (<20ns pulse width, 10j) to boot lgate voltage (lgate) . . . . . . . . -0.3v (dc) to vdd + 0.3v . . . . . . . . . -2.5v (<20ns pulse width, 5j) to vdd + 0.3v all other pins. . . . . . . . . . . . . . . . . . -0.3v to (vdd + 0.3v) open drain outputs, pgood, vr_tt#, clk_en# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to +7v esd rating human body model (tested per jesd22-a114e) . . . . . 2kv machine model (tested per jesd22-a115-a) . . . . . . . 200v latch up (tested per jesd-78b; class 2, level a) . . . 100ma thermal resistance (typical, notes 4, 5) ja (c/w) jc (c/w) 28 ld tqfn package. . . . . . . . . . . 42 5 32 ld tqfn package. . . . . . . . . . . 34 5 maximum junction temperature . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions supply voltage, vdd . . . . . . . . . . . . . . . . . . . . . +5v 5% battery voltage, vin . . . . . . . . . . . . . . . . . . . +4.5v to 25v ambient temperature isl62881chrtz, ISL62881DHRTZ . . . . . -10c to +100c isl62881cirtz . . . . . . . . . . . . . . . . . . -40c to +100c junction temperature isl62881chrtz, ISL62881DHRTZ . . . . . -10c to +125c isl62881cirtz . . . . . . . . . . . . . . . . . . -40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions: v dd = 5v, t a = -40c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +100c. parameter symbol test conditions min (note 7) typ max (note 7) units input power supply +5v supply current i vdd vr_on = 1v 3.2 4.0 ma vr_on = 0v 1 a battery supply current i vin vr_on = 0v 1 a v in input resistance r vin vr_on = 1v 900 k power-on-reset threshold por r v dd rising 4.35 4.5 v por f v dd falling 4.00 4.15 v system and references system accuracy hrtz %error (v cc_core ) no load; closed loop, active mode range vid = 0.75v to 1.50v, -0.5 +0.5 % vid = 0.5v to 0.7375v -8 +8 mv vid = 0.3v to 0.4875v -15 +15 mv irtz %error (v cc_core ) no load; closed loop, active mode range vid = 0.75v to 1.50v -0.8 +0.8 % vid = 0.5v to 0.7375v -10 +10 mv vid = 0.3v to 0.4875v -18 +18 mv v boot hrtz 1.0945 1.100 1.1055 v irtz 1.0912 1.100 1.1088 v maximum output voltage v cc_core(max) vid = [0000000] 1.500 v minimum output voltage (note 6) v cc_core(min) vid = [1111111] 0 v r bias voltage r bias = 147k 1.45 1.47 1.49 v isl62881c, isl62881d
isl62881c, isl62881d 7 fn7596.0 march 8, 2010 channel frequency nominal channel frequency f sw(nom) rf set = 7k , v comp =1v 295 310 325 khz adjustment range 200 500 khz amplifiers current-sense amplifier input offset i fb = 0a -0.15 +0.15 mv error amp dc gain (note 6) a v0 90 db error amp gain-bandwidth product (note 6) gbw c l = 20pf 18 mhz power good and protection monitors pgood low voltage v ol i pgood = 4ma 0.26 0.4 v pgood leakage current i oh pgood = 3.3v -1 1 a pgood delay tpgd clk_enable# low to pgood high 6.3 7.6 8.9 ms ugate driver ugate pull-up resistance (note 6) r ugpu 200ma source current 1.0 1.5 ugate source current (note 6) i ugsrc boot - ugate = 2.5v 2.0 a ugate sink resistance (note 6) r ugpd 250ma sink current 1.0 1.5 ugate sink current (note 6) i ugsnk ugate - phase = 2.5v 2.0 a lgate driver (isl62881c) lgate pull-up resistance (note 6) r lgpu 250ma source current 1.0 1.5 lgate source current (note 6) i lgsrc vccp - lgate = 2.5v 2.0 a lgate sink resistance (note 6) r lgpd 250ma sink current 0.5 0.9 lgate sink current (note 6) i lgsnk lgate - vssp = 2.5v 4.0 a ugate to lgate deadtime t ugflgr ugate falling to lgate rising, no load 23 ns lgate to ugate deadtime t lgfugr lgate falling to ugate rising, no load 28 ns lgate drivers (isl62881d) lgatea and b pull-up resistance (note 6) r lgpu 250ma source current 2.0 3 lgatea and b source current (note 6) i lgsrc vccp - lgatea and b = 2.5v 1.0 a lgatea and b sink resistance (note 6) r lgpd 250ma sink current 1 1.8 lgatea and b sink current (note 6) i lgsnk lgatea and b - vssp = 2.5v 2.0 a ugate to lgatea and b deadtime t ugflgr ugate falling to lgatea and b rising, no load 23 ns lgatea and b to ugate deadtime t lgfugr lgatea and b falling to ugate rising, no load 28 ns electrical specifications operating conditions: v dd = 5v, t a = -40c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +100c. (continued) parameter symbol test conditions min (note 7) typ max (note 7) units isl62881c, isl62881d
isl62881c, isl62881d 8 fn7596.0 march 8, 2010 bootstrap diode forward voltage v f pvcc = 5v, i f = 2ma 0.58 v reverse leakage i r v r = 25v 0.2 a protection overvoltage threshold ov h vsen rising above setpoint for >1ms 150 200 240 mv severe overvoltage threshold ov hs vsen rising for >2s 1.525 1.55 1.575 v oc threshold offset isum- pin current, r comp open circuit 28 30 32 a undervoltage threshold uv f vsen falling below setpoint for >1.2ms -355 -295 -235 mv logic thresholds vr_on input low v il(1.0v) 0.3 v vr_on input high v ih(1.0v) isl62881chrtz 0.7 v v ih(1.0v) isl62881cirtz 0.75 v vid0-vid6 and dprslpvr input low v il(1.0v) 0.3 v vid0-vid6 and dprslpvr input high v ih(1.0v) 0.7 v thermal monitor (isl62881d) ntc source current ntc = 1.3v 53 60 67 a over-temperature threshold v (ntc) falling 1.18 1.2 1.22 v vr_tt# low output resistance r tt i = 20ma 6.5 9 clk_en# output levels clk_en# low output voltage v ol i = 4ma 0.26 0.4 v clk_en# leakage current i oh clk_en# = 3.3v -1 1 a current monitor imon output current i imon isum- pin current = 20a 108 120 132 a isum- pin current = 10a 54 60 66 isum- pin current = 5a 25.5 30 34.5 imon clamp voltage v imonclamp 1.1 1.15 v current sinking capability 275 a inputs vr_on leakage current i vr_on vr_on = 0v -1 0a vr_on = 1v 0 1 a vidx leakage current i vidx vidx = 0v -1 0a vidx = 1v 0.45 1 a dprslpvr leakage current i dprslpvr dprslpvr = 0v -1 0a dprslpvr = 1v 0.45 1 a slew rate slew rate (for vid change) sr 56.5 mv/s notes: 6. limits established by characterization and are not production tested. 7. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications operating conditions: v dd = 5v, t a = -40c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +100c. (continued) parameter symbol test conditions min (note 7) typ max (note 7) units isl62881c, isl62881d
isl62881c, isl62881d 9 fn7596.0 march 8, 2010 gate driver timing diagram simplified application circuits figure 1. isl62881c typical application circuit using dcr sensing pwm ugate lgate 1v 1v t ugflgr t rl t fu t ru t fl t lgfugr (bottom pad) vss fb vsen comp r droop rf set vw rtn vr_on dprslpvr vids rbias clk_en# v+5 vdd imon clk_en# vid<0:6> dprslpvr vr_on pgood r imon vss sense vcc sense imon pgood v+5 vccp isl62881c r bias l v o r sum rn cn ri v in phase ugate boot lgate isum+ isum- vssp vin vin c isl62881c, isl62881d
isl62881c, isl62881d 10 fn7596.0 march 8, 2010 figure 2. isl62881c typical application circuit using resistor sensing figure 3. isl62881d typical application circuit using dcr sensing simplified application circuits (continued) (bottom pad) vss fb vsen comp r droop rf set vw rtn vr_on dprslpvr vids rbias clk_en# v+5 vdd imon clk_en# vid<0:6> dprslpvr vr_on pgood r imon vss sense vcc sense imon pgood v+5 vccp isl62881c r bias cn ri vin phase ugate boot lgate isum+ isum- vssp vin vin l v o r sum rsen gnd fb vsen comp r droop rf set vw rtn vr_on dprslpvr vids r bias clk_en# v+5 v dd imon clk_en# vid<0:6> dprslpvr vr_on pgood r imon vss sense vcc sense imon pgood v+5 vccp isl62881d r bias l v o rsum rn cn ri v in phase ugate boot lgatea isum+ isum- vssp o c v in v in ntc o c vr_tt# vr_tt# lgateb isl62881c, isl62881d
isl62881c, isl62881d 11 fn7596.0 march 8, 2010 figure 4. isl62881d typical applicat ion circuit using resistor sensing simplified application circuits (continued) vss v+5 v dd v+5 vccp isl62881d cn ri isum+ isum- v in v in l v o rsum rsen v in phase ugate boot lgatea vssp lgateb fb vsen comp r droop rf set vw rtn vr_on dprslpvr vids r bias clk_en# imon clk_en# vid<0:6> dprslpvr vr_on pgood r imon vss sense vcc sense imon pgood r bias ntc o c vr_tt# vr_tt# isl62881c, isl62881d
isl62881c, isl62881d 12 fn7596.0 march 8, 2010 theory of operation multiphase r 3? modulator the isl62881c is a single-phase regulator implementing intel ? imvp-6.5 ? protocol. it uses intersil patented r 3? (robust ripple regulator ? ) modulator. the r 3? modulator combines the best features of fixed frequency pwm and hysteretic pwm while eliminating many of their shortcomings. figure 5 conceptually shows the isl62881c r 3? modulator circuit, and figure 6 shows the operation principles. a current source flows from the vw pin to the comp pin, creating a voltage window set by the resistor between between the two pins. this voltage window is called vw window in the following discussion. inside the ic, the modulator uses the master clock circuit to generate the clocks for the slave circuit. the modulator discharges the ripple capacitor c rm with a current source equal to g m v o , where g m is a gain factor. c rm voltage v crm is a sawtooth waveform traversing between the vw and comp voltages. it resets to vw when it hits comp, and generates a one-shot clock signal. the slave circuit has its own ripple capacitor c rs , whose voltage mimics the inductor ripple current. a g m amplifier converts the inductor voltage into a current source to charge and discharge c rs . the slave circuit turns on its pwm pulse upon receiving the clock signal, and the current source charges c rs . when c rs voltage v crs hits vw, the slave circuit turns off the pwm pulse, and the current source discharges c rs . since the isl62881c works with v crs , which is large- amplitude and noise-free synthesized signal, the isl62881c achieves lower phase jitter than conventional hysteretic mode and fixed pwm mode controllers. unlike conventional hysteretic mode converters, the isl62881c has an error amplifier that allows the controller to maintain a 0.5% output voltage accuracy. figure 7 shows the operation principles during load insertion response. the comp voltage rises during load insertion, generating the clock signal more quickly, so the pwm pulse turns on earlier, increasing the effective switching frequency, which allows for higher control loop bandwidth than conventional fixed frequency pwm controllers. the vw voltage rises as the comp voltage rises, making the pwm pulse wider. during load release response, the comp voltage falls. it takes the master clock circuit longer to generate the next clock signal so the pwm pulse is held off until needed. the vw voltage falls as the vw voltage falls, reducing the current pwm pulse width. this kind of behavior gives the isl62881c excellent response speed. figure 5. r 3? modulator circuit crm gmvo master clock vw comp clock r il gm clock phase crs vw s q pwm l co vo vcrm vcrs master clock circuit slave circuit figure 6. r 3? modulator operation principles in steady state comp vcrm pwm vw clock hysteretic window vcrs vw figure 7. r 3? modulator operation principles in load insertion response comp vcrm pwm vcrs vw clock vw isl62881c, isl62881d
isl62881c, isl62881d 13 fn7596.0 march 8, 2010 diode emulation and period stretching isl62881c can operate in diode emulation (de) mode to improve light load efficiency. in de mode, the low-side mosfet conducts when the current is flowing from source to drain and doesn?t not allow reverse current, emulating a diode. as shown in figure 8, when lgate is on, the low-side mosfet carries current, creating negative voltage on the phase node due to the voltage drop across the on-resistance. the isl62881c monitors the current through monitoring the phase node voltage. it turns off lgate when the phase node voltage reaches zero to prevent the inductor current from reversing the direction and creating unnecessary power loss. if the load current is light en ough, as figure 9 shows, the inductor current will reach and stay at zero before the next phase node pulse, and the regulator is in discontinuous conduction mode (dcm). if the load current is heavy enough, the inductor current will never reach 0a, and the regulator is in ccm although the controller is in de mode. figure 9 shows the operation principle in diode emulation mode at light load. the load gets incrementally lighter in the three cases from top to bottom. the pwm on-time is determined by the vw window size, therefore is the same, making the inductor current triangle the same in the three cases. the isl62881c clamps the ripple capacitor voltage v crs in de mode to make it mimic the inductor current. it takes the comp voltage longer to hit v crs , naturally stretching the switching period. the inductor current triangles move further apart from each other such that the inductor current average value is equal to the load current. the reduced switching frequency helps increase light load efficiency. start-up timing with the controller's v dd voltage above the por threshold, the start-up se quence begins when vr_on exceeds the 3.3v logic high threshold. figure 10 shows the typical start-up timing when the isl62881c is configured fo r cpu vr application. the isl62881c uses digital soft-start to ramp up dac to the boot voltage of 1.1v at about 2.5mv/s. once the output voltage is within 10% of the boot voltage for 13 pwm cycles (43s for frequency = 300khz), clk_en# is pulled low and dac slews at 5mv/s to the voltage set by the vid pins. pgood is asserted high in approximately 7ms. similar results occur if vr_on is tied figure 8. diode emulation ugate phase il lgate figure 9. period stretching il il vcrs il vcrs vcrs vw ccm/dcm boundary light dcm deep dcm vw vw figure 10. soft-start waveforms for cpu vr application vdd vr_on dac 800s 2.5mv/s vboot 5mv/s vid command voltage 90% 13 switching cycles clk_en# pgood ~7ms figure 11. soft-start waveforms for gpu vr application vdd vr_on dac 120s 5mv/s vid command voltage 90% 13 switching cycles clk_en# pgood ~7ms isl62881c, isl62881d
isl62881c, isl62881d 14 fn7596.0 march 8, 2010 to v dd , with the soft-start sequence starting 120s after v dd crosses the por threshold. figure 11 shows the typical start-up timing when the isl62881c is configured for gpu vr application. the isl62881c uses digital soft-start to ramp-up dac to the voltage set by the vid pins at 5mv/s. once the output voltage is within 10% of the target voltage for 13 pwm cycles (43s for frequency = 300khz), clk_en# is pulled low. pgood is asserted high in approximately 7ms. similar results occur if vr_on is tied to v dd , with the soft-start sequence starting 120s after v dd crosses the por threshold. voltage regulation and load line implementation after the start sequence, the isl62881c regulates the output voltage to the value set by the vid inputs per table 1. the isl62881c will control the no-load output voltage to an accuracy of 0.5% over the range of 0.75v to 1.5v. a differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die. table 1. vid table vid6 vid5 vid4 vid3 vid2 vid1 vid0 v o (v) 00000001.5000 00000011.4875 00000101.4750 00000111.4625 00001001.4500 00001011.4375 00001101.4250 00001111.4125 00010001.4000 00010011.3875 00010101.3750 00010111.3625 00011001.3500 00011011.3375 00011101.3250 00011111.3125 00100001.3000 00100011.2875 00100101.2750 00100111.2625 00101001.2500 00101011.2375 00101101.2250 00101111.2125 00110001.2000 00110011.1875 00110101.1750 00110111.1625 00111001.1500 00111011.1375 00111101.1250 00111111.1125 01000001.1000 01000011.0875 01000101.0750 01000111.0625 01001001.0500 01001011.0375 01001101.0250 01001111.0125 01010001.0000 01010010.9875 01010100.9750 01010110.9625 01011000.9500 01011010.9375 01011100.9250 01011110.9125 01100000.9000 01100010.8875 01100100.8750 01100110.8625 01101000.8500 01101010.8375 01101100.8250 01101110.8125 01110000.8000 01110010.7875 01110100.7750 01110110.7625 01111000.7500 01111010.7375 01111100.7250 01111110.7125 10000000.7000 10000010.6875 10000100.6750 table 1. vid table (continued) vid6 vid5 vid4 vid3 vid2 vid1 vid0 v o (v) isl62881c, isl62881d
isl62881c, isl62881d 15 fn7596.0 march 8, 2010 as the load current increases from zero, the output voltage will droop from the vid table value by an amount proportional to the load current to achieve the load line. the isl62881c can sense the inductor current through the intrinsic dc resistance (dcr) resistance of the inductors as shown in figure 1 on page 9 or through resistors in series with the inductors as shown in figure 2 on page 10. in both methods, capacitor c n voltage represents the inductor tota l currents. a droop amplifier converts c n voltage into an internal current source with 10000110.6625 10001000.6500 10001010.6375 10001100.6250 10001110.6125 10010000.6000 10010010.5875 10010100.5750 10010110.5625 10011000.5500 10011010.5375 10011100.5250 10011110.5125 10100000.5000 10100010.4875 10100100.4750 10100110.4625 10101000.4500 10101010.4375 10101100.4250 10101110.4125 10110000.4000 10110010.3875 10110100.3750 10110110.3625 10111000.3500 10111010.3375 10111100.3250 10111110.3125 11000000.3000 11000010.2875 11000100.2750 11000110.2625 11001000.2500 11001010.2375 11001100.2250 11001110.2125 11010000.2000 11010010.1875 11010100.1750 table 1. vid table (continued) vid6 vid5 vid4 vid3 vid2 vid1 vid0 v o (v) 11010110.1625 11011000.1500 11011010.1375 11011100.1250 11011110.1125 11100000.1000 11100010.0875 11100100.0750 11100110.0625 11101000.0500 11101010.0375 11101100.0250 11101110.0125 11110000.0000 11110010.0000 11110100.0000 11110110.0000 11111000.0000 11111010.0000 11111100.0000 11111110.0000 table 1. vid table (continued) vid6 vid5 vid4 vid3 vid2 vid1 vid0 v o (v) figure 12. differential sensing and load line implementation x 1 e/a
isl62881c, isl62881d 16 fn7596.0 march 8, 2010 the gain set by resistor r i . the current source is used for load line implementation, current monitor and overcurrent protection. figure 12 shows the load line implementation. the isl62881c drives a current source i droop out of the fb pin, described by equation 1. when using inductor dcr current sensing, a single ntc element is used to compensate the positive temperature coefficient of the copper wind ing thus sustaining the load line accuracy with reduced cost. i droop flows through resistor r droop and creates a voltage drop as shown in equation 2. v droop is the droop voltage required to implement load line. changing r droop or scaling i droop can both change the load line slope. since i droop also sets the overcurrent protection level, it is recommended to first scale i droop based on ocp requirement, then select an appropriate r droop value to obtain the desired load line slope. differential sensing figure 12 also shows the differential voltage sensing scheme. vcc sense and vss sense are the remote voltage sensing signals from the processor die. a unity gain differential amplifier senses the vss sense voltage and adds it to the dac output. the error amplifier regulates the inverting and the non-inverting input voltages to be equal, therefore: rewriting equation 3 and substituting equation 2 gives: equation 4 is the exact equation required for load line implementation. the vcc sense and vss sense signals come from the processor die. the feedback will be open circuit in the absence of the processor. as shown in figure 12, it is recommended to add a ?catch? resistor to feed the vr local output voltage back to the compensator, and add another ?catch? resistor to connect the vr local output ground to the rtn pin. these resistors, typically 10 ~100 , will provide voltage feedback if the system is powered up without a processor installed. ccm switching frequency the r fset resistor between the comp and the vw pins sets the vw windows size, which therefore sets the switching frequency. when the isl62881c is in continuous conduction mode (ccm), the switching frequency is not absolutely constant due to the nature of the r 3? modulator. as explained in ?multiphase r3? modulator? on page 12, the effective switching frequency will increase during load insertion and will decrease during load release to achieve fast response. on the other hand, the switching frequency is relatively constant at steady state. variation is expected when the power stage condition, such as input voltage, output voltage, load, etc. changes. the variation is usually less than 15% and doesn?t have any significant effect on output voltage ripple magnitude. equation 5 gives an estimate of the frequency-setting resistor r fset value. 8k r fset gives approximately 300khz switching frequency. lower resistance gives higher switching frequency. modes of operation table 2 shows the isl62881c operational modes, programmed by the logic status of the dprslpvr pin. the isl62881c enters 1-phase de mode when there is dprslpvr = 1. when the isl62881c is configured for gpu vr application, dprslpvr logic status also controls the output voltage slew rate. the slew rate is 5mv/s for dprslpvr = 0 and is 10mv/s for dprslpvr = 1. dynamic operation when the isl62881c is configured for cpu vr application, it responds to vid changes by slewing to the new voltage at 5mv/s slew rate. as the output approaches the vid command voltage, the dv/dt moderates to prevent overshoot. geyserville-iii transitions commands one lsb vid step (12.5mv) every 2.5s, controlling the effective dv/dt at 5mv/s. the isl62881c is capable of 5mv/s slew rate. when the isl62881c is configured for gpu vr application, it responds to vid changes by slewing to the new voltage at a slew rate set by the logic status on the dprslpvr pin. the slew rate is 5mv/s when dprslpvr = 0 and is 10mv/s when dprslpvr = 1. when the isl62881c is in de mode, it will actively drive the output voltage up when the vid changes to a higher value. it?ll resume de mode operation after reaching the new voltage level. if the load is light enough to warrant dcm, it will enter dcm afte r the inductor current has crossed zero for four consecutive cycles. the isl62881c will remain in de mode when the vid changes to a lower value. the output voltage will decay to the new value and the load will determine the slew rate. during load insertion response, the fast clock function increases the pwm pulse response speed. the i droop 2xv cn r i ------------------ = (eq. 1) v droop r droop i droop = (eq. 2) vcc sense v + droop v dac vss sense + = (eq. 3) vcc sense vss sense ? v dac r droop i droop ? = (eq. 4) table 2. isl62881c modes of operation configuration dprslpvr operational mode voltage slew rate cpu vr application 0 1-phase ccm 5mv/s 11-phase de gpu vr application 0 1-phase ccm 5mv/s 11-phase de10mv/s r fset k () period s () 0.29 ? () 2.65 = (eq. 5) isl62881c, isl62881d
isl62881c, isl62881d 17 fn7596.0 march 8, 2010 isl62881c monitors the vsen pin voltage and compares it to 100ns filtered version. when the unfiltered version is 20mv below the filtered version, the controller knows there is a fast voltage dip due to load insertion, hence issues an additional master clock signal to deliver a pwm pulse immediately. the r 3? modulator intrinsically has voltage feed forward. the output voltage is insensitive to a fast slew rate input voltage change. protections the isl62881c provides overcurrent, undervoltage, and overvoltage protections. the isl62881c determines overcurrent protection (ocp) by comparing the average value of the droop current i droop with an internal current source threshold. it declares ocp when i droop is above the threshold for 120s. a resistor r comp from the comp pin to gnd programs the ocp current source threshold, as well as the overshoot reduction function (to be discussed in later sections), as table 3 shows. it is recommended to use the nominal r comp value. the isl62881c detects the r comp value at the beginning of start-up, and sets the internal ocp threshold accordingly. it remembers the r comp value until the vr_on signal drops below the por threshold. the default ocp threshold is the value when r comp is not populated. it is recommended to scale the droop current i droop such that the default ocp threshold gives approximately the desired ocp level, then use r comp to fine tune the ocp level if necessary. for overcurrent condition above 2.5x the ocp level, the pwm output will immediately shut off and pgood will go low to maximize protection. this protection is also referred to as way-overcurrent protection or fast-overcurrent protection, for short-circuit protections. the isl62881c will declare undervoltage (uv) fault and latch off if the output voltage is less than the vid set value by 300mv or more for 1ms. it?ll turn off the pwm output and de-assert pgood. the isl62881c has two levels of overvoltage protections. the first level of overvoltage protection is referred to as pgood overvoltage protection. if the output voltage exceeds the vid set value by +200mv for 1ms, the isl62881c will decl are a fault and de-assert pgood. the isl62881c takes the same actions for all of the above fault protections: de-assertion of pgood and turn-off of the high-side and low-side power mosfets. any residual inductor curre nt will decay through the mosfet body diodes. these fault conditions can be reset by bringing vr_on low or by bringing v dd below the por threshold. when vr_on and v dd return to their high operating levels, a soft-start will occur. the second level of overvoltage protection is different. if the output voltage exceeds 1.55v, the isl62881c will immediately declare an ov fault, de-assert pgood, and turn on the low-side power mosfets. the low-side power mosfets remain on until the output voltage is pulled down below 0.85v when all power mosfets are turned off. if the output voltage rises above 1.55v again, the protection process is repeated. this behavior provides the maximum amount of protection against shorted high-side power mosfets while preventing output ringing below ground. resetting vr_on cannot clear the 1.55v ovp. only resetting v dd will clear it. the 1.55v ovp is active all the time when the controller is enabled, even if one of the other faults have been declared. this ensures that the processor is protected against high-side power mosfet leakage while the mosfets are commanded off. table 4 summarizes the fault protections. current monitor the isl62881c provides the current monitor function. the imon pin outputs a high-speed analog current source that is 3 times of the droop current flowing out of the fb pin. thus as shown by equation 6. table 3. isl62881c ocp threshold and overshoot reduction function r comp ocp threshold (a) overshoot reduction function min (k ) nominal (k ) max (k ) none none 60 disabled 305 400 410 68 205 235 240 62 155 165 170 54 104 120 130 60 enabled 78 85 90 68 62 66 68 62 45 50 55 54 table 4. fault protection summary fault type fault duration before protection protection action fault reset overcurrent 120s pwm tri-state, pgood latched low vr_on toggle or vdd toggle way-overcurrent (2.5xoc) <2s overvoltage +200mv 1ms undervoltage - 300mv overvoltage 1.55v immediately low-side mosfet on until v core <0.85v, then pwm tri-state, pgood latched low. vdd toggle i imon 3i droop = (eq. 6) isl62881c, isl62881d
isl62881c, isl62881d 18 fn7596.0 march 8, 2010 as figures 1 and 2 show, a resistor r imon is connected to the imon pin to convert the imon pin current to voltage. a capacitor can be paralleled with r imon to filter the voltage information. the imvp-6.5? specification requires that the imon voltage information be referenced to vss sense . the imon pin voltage range is 0v to 1.1v. a clamp circuit prevents the imon pin voltage from going above 1.1v. adaptive body diode conduction time reduction in dcm, the controller turns off the low-side mosfet when the inductor current approaches zero. during on-time of the low-side mosfet, phase voltage is negative and the amount is the mosfet r ds(on) voltage drop, which is proportional to the inductor current. a phase comparator inside the controller monitors the phase voltage during on-time of the low-side mosfet and compares it with a threshold to determine the zero-crossing point of the inductor current. if the inductor current has not reached zero when the low-side mosfet turns off, it?ll flow through the low-side mosfet body diode, causing the phase node to have a larger voltage drop until it decays to zero. if the inductor current has crossed zero and reversed the direction when the low-side mosfet turns off, it?ll flow through the high-side mosfet body diode, causing the phase node to have a spike until it decays to zero. the controller continues monitoring the phase voltage after turning off the low-side mosfet and adjusts the phase comparator threshold voltage accordingly in iterative steps such that the low-side mosfet body diode conducts for approximately 40ns to minimize the body diode-related loss. overshoot reduction function the isl62881c has an optional overshoot reduction function, enabled or disabled by the resistor from the comp pin to gnd, as shown in table 3. when a load release occurs, the energy stored in the inductors will dump to the output capacitor, causing output voltage overshoot. the inductor current freewheels through the low-side mosfet during this period of time. the overshoot reduction function turns off the low-side mosfet during the output voltage overshoot, forcing the inductor current to freewheel through the low-side mosfet body diode. since the body diode voltage drop is much higher than mosfet r ds(on) voltage drop, more energy is dissipated on the low-side mosfet therefore the output voltage overshoot is lower. if the overshoot reduction function is enabled, the isl62881c monitors the comp pin voltage to determine the output voltage overshoot condition. the comp voltage will fall and hit the clamp voltage when the output voltage overshoots. the isl62881c will turn off lgate when comp is being clamped. the low-side mosfet in the power stage will be turned off. when the output voltage has reached its peak and starts to come down, the comp voltage starts to rise and is no longer clamped. the isl62881c will resume normal pwm operation. while the overshoot reduction function reduces the output voltage overshoot, energy is dissipated on the low-side mosfet, causing additional power loss. the more frequent the transient event, the more power loss is dissipated on the low-side mosfet. the mosfet may face severe thermal stress when transient events happen at a high repetitive rate. user discretion is advised when this function is enabled. key component selection r bias the isl62881c uses a resistor (1% or better tolerance is recommended) from the rbias pin to gnd to establish highly accurate reference current sources inside the ic. using r bias = 147k sets the controller for cpu core application and using r bias = 47k sets the controller for gpu core application. do not connect any other components to this pin. do not connect any capacitor to the rbias pin as it will create instability. care should be taken in layout that the resistor is placed very close to the rbias pin and that a good quality signal ground is connected to the opposite side of the r bias resistor. inductor dcr current-sensing network figure 13 shows the inductor dcr current-sensing network. an inductor current flows through the dcr and creates a voltage drop. the inductor has a resistors in r sum connected to the phase-node-side pad and a pcb trace connected to the output-side pad to accurately sense the inductor current by sensing the dcr voltage drop. the sensed current information is fed to the ntc network (consisting of r ntcs , r ntc and r p ) and capacitor c n . r ntc is a negative temperature coefficient (ntc) thermistor, used to temperature-compensate the inductor dcr change. the inductor current information is presented to the capacitor c n . equations 7 through 11 cn rsum rntcs rntc rp dcr l phase io ri isum+ isum- vcn + - figure 13. dcr current-sensing network isl62881c, isl62881d
isl62881c, isl62881d 19 fn7596.0 march 8, 2010 describe the frequency-doma in relationship between inductor total current i o (s) and c n voltage v cn (s): tra ns fe r f u nc t i on a cs (s) always has unity gain at dc. the inductor dcr value increases as the winding temperature increases, giving higher reading of the inductor dc current. the ntc r ntc values decreases as its temperature decreases. proper selections of r sum , r ntcs , r p and r ntc parameters ensure that v cn represents the inductor total dc current over the temperature range of interest. there are many sets of parameters that can properly temperature-compensate the dcr change. since the ntc network and the r sum resistors form a voltage divider, v cn is always a fraction of the inductor dcr voltage. it is recommended to have a higher ratio of v cn to the inductor dcr voltage, so the droop circuit has higher signal level to work with. a typical set of parameters that provide good temperature compensation are: r sum = 1.82k , r p =11k , r ntcs =2.61k and r ntc = 10k (ert-j1vr103j). the ntc netw ork parameters may need to be fine tuned on actual boards. one can apply full load dc current and record th e output voltage reading immediately; then record the output voltage reading again when the board has reached the thermal steady state. a good ntc network can limit the output voltage drift to within 2mv. it is recommended to follow the intersil evaluation board layout and current-sensing network parameters to minimize engineering time. v cn (s) also needs to represent real-time i o (s) for the controller to achieve good transient response. transfer function a cs (s) has a pole sns and a zero l . one needs to match l and sns so a cs (s) is unity gain at all frequencies. by forcing l equal to sns and solving for the solution, equation 12 gives c n value. for example, given r sum = 1.82k , r p = 11k , r ntcs =2.61k , r ntc = 10k , dcr = 1.3m and l = 0.56h, equation 12 gives c n = 0.31f. assuming the compensator design is correct, figure 14 shows the expected load transient response waveforms if c n is correctly selected. when the load current i core has a square change, the output voltage v core also has a square response. if c n value is too large or too small, v cn (s) will not accurately represent real-time i o (s) and will worsen the transient response. figure 15 shows the load transient response when c n is too small. v core will sag excessively upon load insertion and may create a system failure. figure 16 shows the transient response when c n is too large. v core is sluggish in drooping to its final value. there will be excessive overshoot if load insertion occurs during this time, which may potentially hurt the cpu reliability. v cn s () r ntcnet r ntcnet r sum + ------------------------------------------ dcr ?? ?? ?? i o s () a cs s () = (eq. 7) r ntcnet r ntcs r ntc + () r p r ntcs r ntc r p ++ ---------------------------------------------------- = (eq. 8) a cs s () 1 s l ------ - + 1 s sns ------------ - + ---------------------- - = (eq. 9) l dcr l ------------- = (eq. 10) sns 1 r ntcnet r sum r ntcnet r sum + ------------------------------------------ c n -------------------------------------------------------- = (eq. 11) c n l r ntcnet r sum r ntcnet r sum + ------------------------------------------ dcr -------------------------------------------------------------- - = (eq. 12) figure 14. desired load transient response waveforms o i v o figure 15. load transient response when c n is too small o i v o figure 16. load transient response when c n is too large o i v o isl62881c, isl62881d
isl62881c, isl62881d 20 fn7596.0 march 8, 2010 figure 17 shows the output voltage ring back problem during load transient response. the load current i o has a fast step change, but the inductor current i l cannot accurately follow. instead, i l responds in first order system fashion due to the nature of current loop. the esr and esl effect of the output capacitors makes the output voltage v o dip quickly upon load current change. however, the controller regulates v o according to the droop current i droop , which is a real-time representation of i l ; therefore it pulls v o back to the level dictated by i l , causing the ring back problem. this phenomenon is not observed when the output capacitors have very low esr and esl, such as all ceramic capacitors. figure 18 shows two optional circuits for reduction of the ring back. r ip and c ip form an r-c branch in parallel with r i , providing a lower impedance path than r i at the beginning of i o change. r ip and c ip do not have any effect at steady state. through proper selection of r ip and c ip values, i droop can resemble i o rather than i l , and v o will not ring back. the recommended value for r ip is 100 . c ip should be determined through tuning the load transient response waveforms on an actual board. the recommended range for c ip is 100pf~2000pf. however, it should be noted that the r ip -c ip branch may distort the i droop waveform. instead of being triangular as the real inductor current, i droop may have sharp spikes, which may adversely affect i droop average value detection and therefore may affect ocp accuracy. user discretion is advised. c n is the capacitor used to match the inductor time constant. it usually takes the parallel of two (or more) capacitors to get the desired value. figure 18 shows that two capacitors c n.1 and c n.2 are in parallel. resistor r n is an optional component to reduce the v o ring back. at steady state, c n.1 + c n.2 provides the desired c n capacitance. at the beginning of i o change, the effective capacitance is less because r n increases the impedance of the c n.1 branch. as figure 15 explains, v o tends to dip when c n is too small, and this effect will reduce the v o ring back. this effect is more pronounced when c n.1 is much larger than c n.2 . it is also more pronounced when r n is bigger. however, the presence of r n increases the ripple of the v n signal if c n.2 is too small. it is recommended to keep c n.2 greater than 2200pf. r n value usually is a few ohms. c n.1 , c n.2 and r n values should be determined through tuning the load transient response waveforms on an actual board. resistor current-sensing network figure 19 shows the resistor current-sensing network. the inductor has a series current-sensing resistor r sen . r sum and is connected to the r sen pad to accurately capture the inductor current information. the r sum feeds the sensed information to capacitor c n . r sum and c n form a a filter for noise attenuation. equations 13 through 15 gives v cn (s) expressions: figure 17. output voltage ring back problem i o v o i l ring back figure 18. optional circuits for ring back reduction cn.2 rntcs rntc rp ri isum+ isum- rip cip optional vcn cn.1 rn optional + - figure 19. resistor current-sensing network cn rsum dcr l phase io ri isum+ isum- vcn rsen v cn s () r sen i o s () a rsen s () = (eq. 13) a rsen s () 1 1 s sns ------------ - + ---------------------- - = (eq. 14) rsen 1 r sum c n ---------------------------- - = (eq. 15) isl62881c, isl62881d
isl62881c, isl62881d 21 fn7596.0 march 8, 2010 transfer function a rsen (s) always has unity gain at dc. current-sensing resistor r sen value will not have significant variation over-temperature, so there is no need for the ntc network. the recommended values are r sum = 1k and c n = 5600pf. overcurrent protection referring to equation 1 and figures 12, 13 and 19, resistor r i sets the droop current i droop . table 3 shows the internal ocp threshold. it is recommended to design i droop without using the r comp resistor. for example, the ocp threshold is 60a. we will design i droop to be 50a at full load, so the ocp trip level is 1.2x of the full load current. for inductor dcr sensing, equation 16 gives the dc relationship of v cn (s) and i o (s). substitution of equation 16 into equation 1 gives: therefore: substitution of equation 8 and application of the ocp condition in equation 18 gives: where i omax is the full load current, i droopmax is the corresponding droop current. for example, given r sum =1.82k , r p = 11k , r ntcs = 2.61k , r ntc = 10k , dcr = 1.3m , i omax = 22a and i droopmax = 50a, equation 19 gives r i = 873 . for resistor sensing, equation 20 gives the dc relationship of v cn (s) and i o (s). substitution of equation 20 into equation 1 gives equation 21: therefore : substitution of equation 22 and application of the ocp condition in equation 18 give s: where i omax is the full load current, i droopmax is the corresponding droop current. for example, given r sen =1m , i omax = 22a and i droopmax = 50a, equation 23 gives r i = 880 . a resistor from comp to gnd can adjust the internal ocp threshold, providing another dimension of fine-tune flexibility. table 3 shows the detail. it is recommended to scale i droop such that the default ocp threshold gives approximately the desired ocp level, then use r comp to fine tune the ocp level if necessary. load line slope refer to figure 12. for inductor dcr sensing, substitution of equation 17 into equation 2 gives the load line slope expression in equation 24. for resistor sensing, substitution of equation 21 into equation 2 gives the load line slope expression in equation 25 : substitution of equation 18 and rewriting equation 24, or substitution of equation 22 and rewriting equation 25 gives the same result in equation 26 : one can use the full load condition to calculate r droop . for example, given i omax = 22a, i droopmax = 50a and ll = 7m , equation 26 gives r droop = 3.08k . it is recommended to start with the r droop value calculated by equation 26, and fine tune it on the actual board to get accurate load line slope. one should record the output voltage readings at no load and at full load for load line slope calculation. reading the output voltage at lighter load instead of full load will increase the measurement error. current monitor referring to equation 6 for the imon pin current expression. refer to figures 1 and 2, the imon pin current flows through r imon . the voltage across r imon is shown in equation 27: rewriting equation 26 gives equation 28: v cn r ntcnet r ntcnet r sum + ------------------------------------------ dcr ?? ?? ?? i o = (eq. 16) i droop 2 r i ----- r ntcnet r ntcnet r sum + ------------------------------------------ dcr i o = (eq. 17) r i 2r ntcnet dcr i o r ntcnet r sum + () i droop ---------------------------------------------------------------------- = (eq. 18) r i 2 r ntcs r ntc + () r p r ntcs r ntc r p ++ ---------------------------------------------------- dcr i omax r ntcs r ntc + () r p r ntcs r ntc r p ++ ---------------------------------------------------- r sum + ?? ?? ?? i droopmax ------------------------------------------------------------------------------------------------------------------ = (eq. 19) v cn r sen i o = (eq. 20) i droop 2 r i ----- r sen i o = (eq. 21) r i 2r sen i o i droop ---------------------------- = (eq. 22) r i 2r sen i omax i droopmax --------------------------------------- = (eq. 23) ll v droop i o ------------------ - 2r droop r i ---------------------- - r ntcnet r ntcnet r sum + ------------------------------------------ dcr == (eq. 24) ll v droop i o ------------------ - 2r sen r droop r i ------------------------------------------- == (eq. 25) r droop i o i droop ---------------- ll = (eq. 26) v rimon 3i droop r imon = (eq. 27) i droop i o r droop ------------------- ll = (eq. 28) isl62881c, isl62881d
isl62881c, isl62881d 22 fn7596.0 march 8, 2010 substitution of equation 28 into equation 27 gives equation 29: rewriting equation 29 and application of full load condition gives equation 30: for example, given ll = 7m , r droop = 3.08k , v rimon = 999mv at i omax = 22a, equation 30 gives r imon =6.66k . a capacitor c imon can be paralleled with r imon to filter the imon pin voltage. the r imon c imon time constant is the user?s choice. it is recommended to have a time constant long enough such that switching frequency ripples are removed. compensator figure 14 shows the desired load transient response waveforms. figure 20 shows the equivalent circuit of a voltage regulator (vr) with the droop function. a vr is equivalent to a voltage source (= vid) and output impedance z out (s). if z out (s) is equal to the load line slope ll, i.e. constant output impedance, in the entire frequency range, v o will have square response when i o has a square change. intersil provides a microsoft excel-based spreadsheet to help design the compensator and the current sensing network, so the vr achieves constant output impedance as a stable system. figure 23 shows a screenshot of the spreadsheet. a vr with active droop function is a dual-loop system consisting of a voltage loop and a droop loop which is a current loop. however, neither loop alone is sufficient to describe the entire system. the spreadsheet shows two loop gain transfer functions, t1(s) and t2(s), that describe the entire system. fi gure 21 conceptually shows t1(s) measurement set-up and figure 22 conceptually shows t2(s) measurement set-up. the vr senses the inductor current, multiplies it by a gain of the load line slope, then adds it on top of the sensed output voltage and feeds it to the compensator. t(1) is measured after the summing node, and t2(s) is measured in the voltage loop before the summing node. the spreadsheet gives both t1(s) and t2(s) plots. however, only t2(s) can be actually measured on an isl62881c regulator. t1(s) is the total loop gain of the voltage loop and the droop loop. it always has a higher crossover frequency than t2(s) and has more meaning of system stability. t2(s) is the voltage loop gain with closed droop loop. it has more meaning of output voltage response. design the compensator to get stable t1(s) and t2(s) with sufficient phase margin, and output impedance equal or smaller than the load line slope. v rimon 3i o ll r droop --------------------- - r imon = (eq. 29) r imon v rimon r droop 3i o ll ---------------------------------------------- = (eq. 30) figure 20. voltage regulator equivalent i o v o vid z out(s) = ll load vr + - figure 21. loop gain t1(s) measurement set-up q2 q1 l i o c out v o v in gate driver comp mod load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain = channel b channel a network analyzer + - + + figure 22. loop gain t2(s) measurement set-up q2 q1 l i o c out v o v in gate driver comp mod load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain = channel b channel a network analyzer + + + - isl62881c, isl62881d
isl62881c, isl62881d 23 fn7596.0 march 8, 2010 jia wei, jwei@intersil.com, 919-405-3605 attention: 1. "analysis toolpak" add-in is required. to turn on, go to tools--add-ins, and check "analysis toolpak" . 2. green cells require user input controller part number: phase number: 2 vin: 12 volts vo: 1.15 volts full load current: 50 amps estimated full-load efficiency: 87 % number of output bulk capacitors: 3 capacitance of each output bulk capacitor: 470 uf esr of each output bulk capacitor: 4.5 m r1 2.870 k r1 2.87 k esl of each output bulk capacitor: 0.6 nh r2 387.248 k r2 412 k number of output ceramic capacitors: 30 r3 0.560 k r3 0.562 k capacitance of each output ceramic capacitor: 10 uf c1 188.980 pf c1 150 pf esr of each output ceramic capacitor: 3 m c2 498.514 pf c2 390 pf esl of each output ceramic capacitor: 3 nh c3 32.245 pf c3 32 pf switching frequency: 300 khz inductance per phase: 0.36 uh cpu socket resistance: 0.9 m desired load-line slope: 1.9 m desired isum- pin current at full load: 33.1 ua t1 bandwidth: 190khz t2 bandwidth: 52khz (this sets the over-current protection level) t1 phase margin: 63.4 t2 phase margin: 94.7 inductor dcr 0.88 m place the 2nd compensator pole fp2 at: 1.9 rsum 3.65 k tune ki to get the desired loop gain bandwidth rntc 10 k tune the compensator gain factor ki: 1.15 rntcs 2.61 k (recommended ki range is 0.8~2) rp 11 k recommended value user selected value cn 0.294 uf cn 0.294 uf ri 1014.245 ri 1000 operation parameters use user-selected value (y/n)? performance and stability x fs (switching frequency) changing the settings in red requires deep understanding of control loop design compensator parameters current sensing network parameters compensation & current sensing network design for intersil multiphase r^3 regulators for imvp-6.5 recommended value user-selected value operation parameters loop gain, gain curve

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isl62881c, isl62881d 24 fn7596.0 march 8, 2010 optional slew rate co mpensation circuit for 1-tick vid transition during a large vid transition, the dac steps through the vids at a controlled slew rate of 2.5s or 1.25s per tick (12.5mv), controlling output voltage v core slew rate at 5mv/s or 10mv/s. figure 24 shows the waveforms of 1-tick vid transition. during 1-tick vid transition, the dac output changes at approximately 15mv/s slew rate, but the dac cannot step through multiple vids to control the slew rate. instead, the control loop response speed determines v core slew rate. ideally, v core will follow the fb pin voltage slew rate. however, the controller senses the inductor current increase during the up transition, as the i droop_vid waveform shows, and will droop the output voltage v core accordingly, making v core slew rate slow. similar behavior occurs during the down transition. to c o n t r o l v core slew rate during 1-tick vid transition, one can add the r vid -c vid branch, whose current i vid cancels i droop_vid . when v core increases, the time domain expression of the induced i droop change is as shown in equation 31 : where c out is the total output capacitance. in the meantime, the r vid -c vid branch current i vid time domain expression is as shown in equation 32: it is desired to let i vid (t) cancel i droop_vid (t). so there are : and : the result is: and : for example: given ll = 7m , r droop = 3.08k , c out = 500f, dv core /dt = 10mv/s and dv fb /dt = 15mv/s, equation 35 gives r vid = 3.08k and equation 36 gives c vid = 757pf. it?s recommended to select the calculated r vid value and start with the calculated c vid value and tweak it on the actual board to get the best performance. during normal transient response, the fb pin voltage is held constant, therefore is virtual ground in small signal sense. the r vid -c vid network is between the virtual ground and the real ground, and hence has no effect on transient response. voltage regulator thermal throttling figure 25 shows the thermal throttling feature with hysteresis. an ntc network is connected between the ntc pin and gnd. at low temperature, sw1 is on and sw2 connects to the 1.20v side. the total current flowing out of the ntc pin is 60a. the voltage on ntc pin is higher than the thresh old voltage of 1.20v and the comparator output is low. vr_tt# is pulled up by the external resistor. figure 24. optional slew rate compensation circuit for1-tick vid transition x 1 e/a dac vid<0:6> rdroop idroop_vid vdac fb comp vcore vss sense vids rtn vss internal to ic r vid c vid vid<0:6> vfb vcore i vid idroop_vid ivid optional i droop t () c out ll r droop ------------------------- - dv core dt ------------------ - 1e t ? c out ll -------------------------- - ? ?? ?? ?? ?? = (eq. 31) i vid t () c vid dv fb dt ------------ 1e t ? r vid c vid -------------------------------- ? ?? ?? ?? ?? = (eq. 32) c vid dv fb dt ------------ c out ll r droop ------------------------- - dv core dt ------------------ - = (eq. 33) r vid c vid c out ll = (eq. 34) r vid r droop = (eq. 35) c vid c out ll r droop ------------------------- - dv core dt ------------------ - dv fb dt ------------ ------------------- = (eq. 36) isl62881c, isl62881d
isl62881c, isl62881d 25 fn7596.0 march 8, 2010 when temperature increases, the ntc thermistor resistance decreases so the ntc pin voltage drops. when the ntc pin voltage drops below 1.20v, the comparator changes polarity and turns sw1 off and throws sw2 to 1.24v. this pulls vr_tt# low and sends the signal to start thermal throttle. there is a 6a current reduction on ntc pin and 40mv voltage increase on threshold voltage of the comparator in this state. the vr_tt# signal will be used to change the cpu operation and decrease the power consumption. when the temperature drops down, the ntc thermistor voltage will go up. if ntc voltage increases to above 1.24v, the comparator will flip back. the external re sistance difference in these two conditions is shown in equation 37: one needs to properly select the ntc thermistor value such that the required temperature hysteresis correlates to 2.96k resistance change. a regular resistor may need to be in series with th e ntc thermistor to meet the threshold voltage values. for example, given panasonic ntc thermistor with b = 4700, the resistance will drop to 0.03322 of its nominal at +105c, and drop to 0.03956 of its nominal at +100c. if the required temperature hysteresis is +105c to +100c, the required resistance of ntc will be as shown in equation 38: therefore, a larger value thermistor such as 470k ntc should be used. at +105c, 470k ntc resistance becomes (0.03322 470k )=15.6k . with 60a on the ntc pin, the voltage is only (15.6k 60a) = 0.937v. this value is much lower than the threshold voltage of 1.20v. therefore, a regular resistor needs to be in series with the ntc. the required resistance can be calculated by equation 39: 4.42k is a standard resistor value. therefore, the ntc branch should have a 470k ntc and 4.42k resistor in series. the part number for the ntc thermistor is ertj0ev474j. it is a 0402 package. ntc thermistor will be placed in the hot spot of the board. layout guidelines table 5 shows the layout considerations. the designators refer to the re ference designs shown in figures 26 and 27. ntc r ntc - + v ntc - + vr_tt# 1.24v 54a internal to isl62881c figure 25. circuitry associated with the thermal throttling feature of the isl62881c r s 60a 1.20v sw1 sw2 1.24v 54 a --------------- - 1.20v 60 a --------------- - ? 2.96k = (eq. 37) (eq. 38) 2.96k 0.03956 0.03322 ? () ----------------------------------------------------- - 467k = (eq. 39) 1.20v 60 a --------------- - 15.6k ? 4.4k = table 5. layout considerations name layout consideration gnd create analog ground plane underneat h the controller and the analog signal processing components. don?t let the power ground plane overlap with the analog ground pl ane. avoid noisy planes/tra ces (e.g.: phase node) from crossing over/overlapping with the analog plane. clk_en# no special consideration. pgood no special consideration rbias place the r bias resistor (r 16 ) in general proximity of the controller. low impedance connection to the analog ground plane. vr_tt# no special consideration. ntc the ntc thermistor (r9) needs to be placed close to the thermal source that is monitor to determine thermal throttling. usually it?s placed close to phase-1 high-side mosfet. vw place capacitor (c4) across vw and comp in close proximity of the controller. comp place compensator components (c3, c5, c6 r7, r11, r10 and c11) in general proximity of the controller. fb isl62881c, isl62881d
isl62881c, isl62881d 26 fn7596.0 march 8, 2010 vsen place the vsen/rtn filter (c12, c13) in close proximity of the controller for good decoupling. rtn vdd a capacitor (c16) decouples it to gnd. place it in close proximity of the controller. imon place the filter capacitor (c21) close to the cpu. isum- place the current sensing circuit in general proximity of the controller. place c82 very close to the controller. place ntc thermistors r 42 next to inductor (l1) so it senses the inductor temperature correctly. the power stage sends a pair of vsum+ and vsum- signals to the controller. run these two signal traces in parallel fashion with decent width (>20mil). important: sense the inductor current by rout ing the sensing circuit to the inductor pads. route r 63 to the phase-node side pad of in ductor l1. route the other current sensing trace to the output side pad of inductor l1. if possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. if no via is al lowed on the pad, consider routing the tr aces into the pads from the inside of the inductor. the following drawings show the two preferred ways of routin g current sensing traces. isum+ vin a capacitor (c17) decouples it to gnd. pl ace it in close proximity of the controller. boot use decent wide trace (> 30mil). avoid any sensitive an alog signal trace from crossing over or getting close. ugate run these two traces in parallel fashion with decent width (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. reco mmend routing phase trace to the high-side mosfet (q2 and q8) source pins instead of general phase node copper. phase vssp run these two traces in parallel fashion with decent width (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. reco mmend routing vssp to the low-side mo sfet (q3 and q9) source pins instead of general power ground pl ane for better performance. lgate or lgatea and lgateb vccp a capacitor (c22) decouples it to gnd. place it in close proximity of the controller. vid0~6 no special consideration. vr_on no special consideration. dprslpvr no special consideration. phase node minimize phase node copper area . don?t let the phase node copper overlap with/getting close to other sensitive traces. cut the power ground plane to av oid overlapping with phase node copper. minimize the loop consisting of input capacitor, high-sid e mosfets and low-side mosfet s (e.g.: c27, c33, q2, q8, q3 and q9). table 5. layout consid erations (continued) name layout consideration inductor current- sensing traces vias inductor current- sensing traces isl62881c, isl62881d
isl62881c, isl62881d 27 fn7596.0 march 8, 2010 0.047uf 0.033uf 0.27uf 11k ntc optional ---- dnp dnp -------- -------- ---- optional ------- ---- dnp ---- ------- ------------ place near l1 ---- optional ---- ----- 1000pf ---- dnp ---- ------------ 330pf 2.37k dnp -----> irf7832 irf7821 optional ----- route ugate trace in parallel with the phase trace going to the source of q2 route lgate trace in parallel with the vssp trace going to the source of q3 10k 0.56uh 1.3mohm 220uf 220uf 7mohm 7mohm dnp dnp dnp dnp 22uf 22uf 10uf 10uf 1.07k 0.1uf 7.15k 3.48k 47pf 390pf 390pf 261k 8.66k 47.5k 1.82k 2.61k layout note: isl62881c r38 r42 vsssense imon c20 c61 vcore c60 c52 c52 c40 c41 c54 c55 c56 c59 +5v 22 20 1uf c21 c83 r110 pgood +3.3v dprslpvr 25 c13 r4 r18 +5v 27 r37 r40 0 c22 r6 r16 29 23 1000pf 10 q2 q3 c33 10uf c27 10uf c24 56uf 0.22uf c30 0 vid4 r50 r63 r41 vin 1 c17 1uf c82 r30 2 15 14 13 12 11 10 7 6 5 1 4 3 17 19 28 24 u6 21 9 8 16 18 0 c4 r7 r17 10 vin vid0 vid1 vid3 vid5 vid6 vid2 vr_on vcore vsssense c3 0.22uf r11 r10 c16 c6 r56 l1 c18 r109 c81 r20 vccsense c12 26 r19 1.91k c11 ep vid6 vid5 vid4 dprslpvr vccp lgate vssp vr_on rbias vw clk_en# comp fb vsen rtn isum- isum+ vdd vin imon boot ugate phase vid0 vid1 vid2 vid3 pgood out out in in in in in in in in in in in in in in in in out in in figure 26. gpu application reference design isl62881c, isl62881d
isl62881c, isl62881d 28 fn7596.0 march 8, 2010 9.09k 226k 390pf 56pf 715 1000pf 1.33k 909 0.047uf 0.22uf 7.68k 0.047uf 1.82k 1.1mohm 0.45uh 1000pf optional optional -------- -------- ---- ---- ---- ------- dnp dnp dnp ---- 10uf place near l1 330pf 2.61k irf7832 irf7832 ntc 10k 0.1uf 11k -----> 330uf 330uf with the phase trace going to layout note: 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf route lgate trace in parallel irf7821 ---- ----- ----------- dnp dnp ----- ---- optional ------- ---- optional ----------- ---- the source of q3 and q9 the source of q2 and q8 10uf 10uf route ugate trace in parallel with the vssp trace going to 10 6 24 r7 r18 c6 c12 1000pf 10 c18 11 imon vin vccsense vsssense r63 r56 r38 27 26 vcore c39 q2 l1 c20 r42 22 8 9 21 +5v r40 r50 c21 0 u6 25 28 17 3 4 1 5 7 10 20 23 2 r10 147k r16 vid4 dprslpvr vr_on vid6 vid5 vid3 c22 1uf q9 10uf c33 10uf 0 56uf vin +5v c27 c24 0.22uf c52 c56 c70 c47 c63 c40 c71 c41 c74 c48 c49 c59 c75 c61 c54 c55 c50 c42 c43 c64 c65 c66 c68 vcore r6 c4 c3 r17 1 0 16 15 13 0.22uf r109 c81 vid2 pgood clk_en# r11 c82 r30 q3 c67 c60 r41 +3.3v c30 r4 c13 c83 r110 r37 14 19 18 c11 r20 29 vid1 vid0 12 c17 1uf c16 vsssense isl62881c 1.91k r23 1.91k r19 ep vid6 vid5 vid4 dprslpvr vccp lgate vssp vr_on rbias vw clk_en# comp fb vsen rtn isum- isum+ vdd vin imon boot ugate phase vid0 vid1 vid2 vid3 pgood out out out in in in in in in in in out in in in in in in in in in in figure 27. cpu application reference design isl62881c, isl62881d
isl62881c, isl62881d 29 fn7596.0 march 8, 2010 cpu application reference de sign bill of materials qty reference value description ma nufacturer part number package 1 c11 1000pf multilayer cap, 16v, 10% generic h1045-00102-16v10 sm0603 1 c12 330pf multilayer cap, 16v, 10% generic h1045-00331-16v10 sm0603 1 c13 1000pf multilayer cap, 16v, 10% generic h1045-00102-16v10 sm0603 2 c16, c22 1f multilayer cap, 16v, 20% generic h1045-00105-16v20 sm0603 1 c18 0.22f multilayer cap, 16v, 10% generic h1045-00224-16v10 sm0603 1 c20 0.1f multilayer cap, 16v, 10% generic h1045-00104-16v10 sm0603 1 c21 0.047f multilayer cap, 16v, 10% generic h1045-00473-16v10 sm0603 2 c17, c30 0.22f multilayer cap, 25v, 10% generic h1045-00224-25v10 sm0603 1 c24 56f radial sp series cap, 25v, 20% sanyo 25sp56m case-cc 2 c27, c33 10f multilayer cap, 25v, 20% generic h1065-00106-25v20 sm1206 1 c3 390pf multilayer cap, 16v, 10% generic h1045-00391-16v10 sm0603 2 c39, c52 330f spcap, 2v, 4m panasonic eexsx0d331e4 polymer cap, 2.5v, 4.5m kemet t520v337m2r5a(1)e4r5-6666 1 c4 1000pf multilayer cap, 16v, 10% generic h1045-00102-16v10 sm0603 30 c40-c43, c47-c50, c53-c56, c59, c75, c78 10f multilayer cap, 6.3v, 20% taiyo murata kyocera tdk jmk212bj106mg-t grm21br60j106me19 cm21x5r106m06at c2012x5r0j106mt009n sm0805 1 c6 56pf multilayer cap, 16v, 10% generic h1045-00560-16v10 sm0603 1 c82 0.047f multilayer cap, 16v, 10% generic h1045-00473-16v10 sm0603 0c81, c83 dnp 1 l1 0.45h inductor, inductance 20%, dcr 7% panasonic nec-tokin etqp4lr45xfc mpcg1040lr45 10mmx10mm 1 q2 n-channel power mosfet ir irf7821 pwrpakso8 2 q3, q9 n-channel power mosfet ir irf7832 pwrpakso8 1 r10 715 thick film chip resistor, 1% generic h2511-07150-1/16w1 sm0603 1 r11 1.33k thick film chip resistor, 1% generic h2511-01331-1/16w1 sm0603 1 r16 147k thick film chip resistor, 1% generic h2511-01473-1/16w1 sm0603 2 r17, r18 10 thick film chip resistor, 1% generic h2511-00100-1/16w1 sm0603 2 r19, r23 1.91k thick film chip resistor, 1% generic h2511-01911-1/16w1 sm0603 3 r20, r40, r56 0 thick film chip resistor, 1% generic h2511-00r00-1/16w1 sm0603 1 r30 909 thick film chip resistor, 1% generic h2511-09090-1/16w1 sm0603 1 r37 1 thick film chip resistor, 1% generic h2511-01r00-1/16w1 sm0603 1 r38 11k thick film chip resistor, 1% generic h2511-01102-1/16w1 sm0603 1 r41 2.61k thick film chip resistor, 1% generic h2511-02611-1/16w1 sm0603 1 r42 10k ntc thermistor, 10k ntc panasonic ert-j1vr103j sm0603 1 r50 7.68k thick film chip resistor, 1% generic h2511-07681-1/16w1 sm0603 isl62881c, isl62881d
isl62881c, isl62881d 30 fn7596.0 march 8, 2010 1 r6 9.09k thick film chip resistor, 1% generic h2511-09091-1/16w1 sm0603 1 r63 1.82k thick film chip resistor, 1% generic h2511-01821-1/16w1 sm0805 1 r7 226k thick film chip resistor, 1% generic h2511-02263-1/16w1 sm0603 0 r109, r110, r4, r8, r9 dnp 1 u6 imvp-6.5 pwm controller intersil isl62881chrtz qfn-28 cpu application reference de sign bill of materials (continued) qty reference value description ma nufacturer part number package gpu application reference design bill of materials qty reference value description ma nufacturer part number package 1 c11 390pf multilayer cap, 16v, 10% generic h1045-00391-16v10 sm0603 1 c12 330pf multilayer cap, 16v, 10% generic h1045-00331-16v10 sm0603 1 c13 1000pf multilayer cap, 16v, 10% generic h1045-00102-16v10 sm0603 2 c16, c22 1f multilayer cap, 16v, 20% generic h1045-00105-16v20 sm0603 1 c18 0.27f multilayer cap, 16v, 10% generic h1045-00274-16v10 sm0603 1 c20 0.1f multilayer cap, 16v, 10% generic h1045-00104-16v10 sm0603 2 c17, c30 0.22f multilayer cap, 25v, 10% generic h1045-00224-25v10 sm0603 1 c21 0.047f multilayer cap, 16v, 10% generic h1045-00473-16v10 sm0603 1 c24 56f radial sp series cap, 25v, 20% sanyo 25sp56m case-cc 2 c27, c33 10f multilayer cap, 25v, 20% generic h1065-00106-25v20 sm1206 1 c3 390pf multilayer cap, 16v, 10% generic h1045-00391-16v10 sm0603 1 c39, c52 220f spcap, 2v, 7m panasonic eexsx0d221e7 1 c4 1000pf multilayer cap, 16v, 10% generic h1045-00102-16v10 sm0603 2 c40, c41 22f multilayer cap, 6.3v, 20% taiyo murata kyocera tdk jmk212bj226mg-t grm21bc80j226m cm21x5r226m04at c2012x5r0j226mt009n sm0805 2 c54, c55 10f multilayer cap, 6.3v, 20% taiyo murata kyocera tdk jmk212bj106mg-t grm21br60j106me19 cm21x5r106m06at c2012x5r0j106mt009n sm0805 1 c6 47pf multilayer cap, 16v, 10% generic h1045-00470-16v10 sm0603 1 c82 0.033f multilayer cap, 16v, 10% generic h1045-00333-16v10 sm0603 0c56, c59- c61, c81, c83 dnp 1 l1 0.56h inductor, inductance 20%, dcr 7% panasonic nec-tokin etqp4lr56afc mpcg1040lr56 10mmx10mm 1 q2 n-channel power mosfet ir irf7821 pwrpakso8 1 q3 n-channel power mosfet ir irf7832 pwrpakso8 1 r10 2.37k thick film chip resistor, 1% generic h2511-02371-1/16w1 sm0603 1 r11 3.48k thick film chip resistor, 1% generic h2511-03481-1/16w1 sm0603 isl62881c, isl62881d
isl62881c, isl62881d 31 fn7596.0 march 8, 2010 1 r16 47.5k thick film chip resistor, 1% generic h2511-04752-1/16w1 sm0603 2 r17, r18 10 thick film chip resistor, 1% generic h2511-00100-1/16w1 sm0603 1 r19 1.91k thick film chip resistor, 1% generic h2511-01911-1/16w1 sm0603 3 r20, r40, r56 0 thick film chip resistor, 1% generic h2511-00r00-1/16w1 sm0603 1 r30 1.07k thick film chip resistor, 1% generic h2511-01071-1/16w1 sm0603 1 r37 1 thick film chip resistor, 1% generic h2511-01r00-1/16w1 sm0603 1 r38 11k thick film chip resistor, 1% generic h2511-01102-1/16w1 sm0603 1 r41 2.61k thick film chip resistor, 1% generic h2511-02611-1/16w1 sm0603 1 r42 10k ntc thermistor, 10k ntc panasonic ert-j1vr103j sm0603 1 r50 7.15k thick film chip resistor, 1% generic h2511-07151-1/16w1 sm0603 1 r6 8.66k thick film chip resistor, 1% generic h2511-08661-1/16w1 sm0603 1 r63 3.65k thick film chip resistor, 1% generic h2511-03651-1/16w1 sm0805 1 r7 261k thick film chip resistor, 1% generic h2511-02613-1/16w1 sm0603 0 r109, r110, r4, r8, r9 dnp 1 u6 imvp-6.5 pwm controller intersil isl62881chrtz qfn-28 gpu application reference design bill of materials (continued) qty reference value description ma nufacturer part number package isl62881c, isl62881d
isl62881c, isl62881d 32 fn7596.0 march 8, 2010 typical performance figure 28. isl62881ccpueval2zevaluation board ccm efficiency, vid = 0.9v, v in1 =8v, v in2 = 12.6v and v in3 =19v figure 29. isl62881ccpueval2zevaluation board de mode efficiency, vid = 0.9v, v in1 =8v, v in2 = 12.6v and v in3 = 19v figure 30. cpu application ccm load line, vid = 0.9v, v in1 =8v, v in2 = 12.6v and v in3 = 19v figure 31. cpu mode clk_en# delay, v in = 19v, i o = 0a, vid = 1.2v, ch1: phase1, ch2: v o , ch4: clk_en# figure 32. cpu mode soft-start, v in = 19v, i o = 0a, vid = 1.2v, ch1: phase, ch2: v o figure 33. gpu mode soft-start, v in = 19v, i o = 0a, vid = 1.2v, ch1: phase, ch2: v o 70 72 74 76 78 80 82 84 86 88 90 0 2 4 6 8 10121416182022 i out (a) e f f i c i e n c y ( % ) v in = 8v v in = 19v v in = 12v 70 72 74 76 78 80 82 84 86 88 0.1 1.0 10.0 i out (a) e f f i c i e n c y ( % ) v in = 8v v in = 19v v in = 12v 0.80 0.81 0.82 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.90 0.91 10 12 14 16 18 20 22 i out (a) v out ( v ) 02468 v in = 19v v in = 12v v in = 8v isl62881c, isl62881d
isl62881c, isl62881d 33 fn7596.0 march 8, 2010 figure 34. cpu mode shut down, v in =19v, i o = 0a, vid = 1.2v, ch1: phase, ch2: v o figure 35. gpu mode shut down, v in = 19v, i o = 0a, vid = 1.2v, ch1: phase, ch2: v o figure 36. ccm steady state, cpu mode, v in =8v, i o = 1a, vid = 1.2375v, ch1: phase, ch2: v o figure 37. dcm steady state, cpu mode, v in = 12v, i o = 1a, vid = 1.075v, ch1: phase1, ch2: v o , ch3: comp, ch4: lgate figure 38. gpu mode reference design loop gain t2(s) measurement result figure 39. imon, vid = 1.2375 typical performance (continued) gain phase margin 0 100 200 300 400 500 600 700 800 900 1000 02468101214161820 i out (a) imon-vss sense (mv) v in = 8v v in = 19v target v in = 12v isl62881c, isl62881d
isl62881c, isl62881d 34 fn7596.0 march 8, 2010 figure 40. load transient response with overshoot reduction function disabled, gpu mode, v in =12v, vid = 0.9v, i o = 12a/22a, di/dt = ?fastest? figure 41. load transient response with overshoot reduction function disabled, gpu mode, v in =12v, vid = 0.9v, i o = 12a/22a, di/dt = ?fastest? figure 42. load transient response with overshoot reduction function disabled, gpu mode, v in =12v, vid = 0.9v, i o = 12a/22a, di/dt = ?fastest? figure 43. load transient response with overshoot reduction function disabled, gpu mode, v in =12v, vid = 0.9v, i o = 12a/22a, di/dt = ?fastest? figure 44. cpu mode vid transition, dprslpvr = 0, i o =2a, vid = 1.2375v/1.0375v, ch2: v o , ch3: vid4 figure 45. gpu mode vid transition, dprslpvr = 0, i o =2a, vid = 1.2375v/1.0375v, ch2: v o , ch3: vid4 typical performance (continued) isl62881c, isl62881d
isl62881c, isl62881d 35 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7596.0 march 8, 2010 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: isl62881c , isl62881d to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php figure 46. cpu mode vid transition, dprslpvr = 1, i o =2a, vid = 1.2375v/1.0375v, ch2: v o , ch3: vid4 figure 47. gpu mode vid transition, dprslpvr = 1, i o =2a, vid = 1.2375v/1.0375v, ch2: v o , ch3: vid4 typical performance (continued) revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 3/8/10 fn7596.0 initial release.
isl62881c, isl62881d 36 fn7596.0 march 8, 2010 isl62881c, isl62881d package outline drawing l28.4x4 28 lead thin quad flat no-lead plastic package rev 0, 9/06 typical recommended land pattern detail "x" top view bottom view notes: 1. controlling dimensions are in mm. dimensions in ( ) for reference only. 2. unless otherwise specified, tolerance : decimal 0.05 angular 2 3. dimensioning and tolerancing conform to amse y14.5m-1994 . 4. bottom side pin#1 id is diepad chamfer as shown. 5. tiebar shown (if present) is a non-functional feature. pin 1 index area 4 . 00 0 ~ 0 . 05 5 0 . 10 pin #1 index area chamfer 0 . 400 x 45? 2 . 50 2 . 50 3 . 20 a package boundary 4 . 00 0 . 40 0 . 20 ?0 . 0 0 . 40 0 . 20 ref 0 . 00 - 0 . 05 see detail x'' seating plane (28x 0 . 60) (0 . 40) (28x 0 . 20) (2 . 50) (2 . 50) (3 . 20) (3 . 20) 0 . 4 x 6 = 2.40 ref 3 . 20 0 . 4 x 6 = 2 . 40 ref max. 0 . 80 (0 . 40) b side view c c 0 . 20 ref 0 . 08 c 0 . 10 c 0 . 10 m c a b 2x 14 8 7 1 28 22 21 15
isl62881c, isl62881d 37 fn7596.0 march 8, 2010 isl62881c, isl62881d package outline drawing l32.5x5e 32 lead thin quad flat no-lead plastic package rev 0, 03/09 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal ? 0.0 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view ( 4.80 ) (3.70 ) ( 32 x 0.60) (32x 0.25) ( 28x 0.50) ( 4.80 ) ( 3.50) ( 3.50) c 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 25 pin #1 index area 32 3.50 28x 0.50 exp. dap 8 1 24 16 32x 0.40 9 6 3.50 3.70 0.10 32x 0.25 a mc b 4 3.70 exp. dap 17 5.00 a b 5.00 (4x) 0.15 6 pin 1 index area max 0.80 see detail "x" seating plane 0.08 0.10 c c c side view

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